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Slave Port Interface
8.4.2
8.4.2.1
Slave Port Interface register descriptions
Slave Port Mailbox Register n
The slave port is the main communication channel between the system master and the MMA955xL.
SP_MB0 through SP_MB31 are bidirectional mailboxes and can be software-configured to support any
number of applications. Each mailbox can be read/written by both the CPU and the sensor master. Reads
by both CPU and master are non-blocking and can occur simultaneously. CPU writes may be delayed a
cycle to allow master writes time to complete.
NOTE
Simultaneous writes represent a hazard condition. Developers are
encouraged to restrict write access to either CPU or sensor master on a
register-by-register basis.
The write status registers (SP_WSTS0, 1, 2, and 3) can be used to notify the CPU that the master has
written to one or more mailbox registers. Whenever any of the mailbox registers has been written, the bit
corresponding to that register in the SP_WSTS x registers will be set. The slave port can be configured to
generate an interrupt when this occurs.
SP_MB31 and SP_MB15 can be programmed via the SP_SCL[WWUP] bits to operate as a special
“wake-up” register that will wake the CPU from STOP mode when written. This operation can be extended
to all of the SP_MB X registers or none, as desired.
7
6
5
4
3
2
1
0
Read
DATA[7:0]
Write
Reset
0
0
0
0
0
0
0
0
= Unimplemented or reserved
Figure 8-5. Slave Port Mailbox Register n (SP_MBn)
Table 8-6. Slave Port Mailbox Register n (SP_MBn) field descriptions
Bit(s)
7-0
Field
DATA
See detailed description above.
Description
MMA955xL Intelligent, Motion-Sensing Platform Hardware Reference Manual, Rev. 1.0
Freescale Semiconductor, Inc.
125
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